[time-nuts] GPS SDR (was: FE-.5680A trimming resolution)
attila at kinali.ch
Wed Feb 1 20:22:35 UTC 2012
On Wed, 1 Feb 2012 11:49:51 -0800
Peter Monta <pmonta at gmail.com> wrote:
> One possible inexpensive design:
> - RF input passively split three ways, with LC filters for the three
> channels: L5/E5, L2, and L1/E1/Glonass
> - For each channel, a downconverter (Maxim MAX2121) feeding a ~65 Ms/s
> ADC (e.g. MAX19505)
> - A low-cost FPGA (e.g. Spartan-6) that quantizes the channels to 2
> bits, does AGC, assembles Ethernet packets
> - Ethernet PHY, power (PoE?), etc.
Heh..That's pretty much the design i thought of, though using a higher
sampling frequency (100 to 200Msps) which would allow to coherently
decode the E5a and E5b signals together. There is an ADC from National
that can do 200Msps for 20 bucks, with FPGA friendly parallel output
> Is there a publically-available antenna design that's easy to
> fabricate, has a stable phase center, covers 1100--1600 MHz, and has a
> good pattern over this band with low cross-polarization? Even a large
> choke-ring design would be okay if it's fully specified.
That's a good question. I don't know. I think a dual band patch antenna
design would work (two stacked patches). This would be easy to fabricate
with very good horizontal tolerances (just use PCBs). But i have neither
designed such an antenna, simulated or even build and tested...
But the other designs i've seen are much more difficult to build with
home tools or need tuning which is not easily done if you don't have
access to good equipment.
Why does it take years to find the answers to
the questions one should have asked long ago?
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