[time-nuts] Brooks Shera

[Bruce Griffiths]

There are essentially 4 clock domains in the circuit

1) PPS

2) Divided down 10MHz (~300kHz)

3) 24 MHz

4) The microprocessor internal clock ( the micro probably has internal 
synchronisers for at least some external inputs).
Depending on internal delays and jitter this may be regarded as 
synchronous with the 24MHz signal.

The required fix is relatively simple:

1) use a 2 stage synchroniser (clocked at 24MHz) plus an additional FF 
to generate a 1 clock period duration pulse on each leading edge of the 
PPS input

2) use a 2 stage synchroniser (clocked at 24MHz) plus an additional FF 
to generate a 1 clock period duration pulse on each leading edge of the 
~300KHz input

The synchronised PPS and 300KHz signals are now in the 24MHz clock 
domain and can be used to generate a synchronised gate (or enable) 
signal with a duration equal to the time interval between the 
synchronised PPS and the next synchronised  300KHz pulses for a ripple 
(or synchronous) count chain.


Bruce

EWKehren at aol.com wrote:
> Bruce, would you mind being more specific and offer a solution.
> Thanks   Bert Kehren
>
>
> In a message dated 3/25/2013 7:09:41 A.M. Eastern Daylight Time,
> bruce.griffiths at xtra.co.nz writes:
>
> The lack  of synchronisers when crossing clock domains is a design flaw
> that should  be corrected.
>
> Bruce
>
>