[time-nuts] Metastability (was Brooks Shera)

Bruce Griffiths bruce.griffiths at xtra.co.nz
Mon Mar 25 16:38:01 EDT 2013

Both edges of the 24MHz clock gating pulse are asynchronous with respect 
to the signal being gated.
Metastability can result with clock pulse widths that lie within a 
critical range.


Chris Albertson wrote:
> On Mon, Mar 25, 2013 at 12:45 PM, David McGaw<n1hac at alum.dartmouth.org>  wrote:
>> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
>> early 80's.  By the third 7400 generation (F/AS/ALS) the problem was well
>> known with parameters available and the logic fairly hard to it
> I think this is all moot because as I just wrote in another email the
> PPS signal never gets out of the 74hct4046 chip.   What gets out is
> the output of  "Phase Detector #3".  You've have to know in some
> detail how the 4046 chips' PD3 works.
> Chris Albertson
> Redondo Beach, California
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