[time-nuts] Metastability (was Brooks Shera)

[Bob Camp]

Hi

With the 24 MHz clock in the circuit, and the logic families shown, the most
likely metastability issues are edge rather than clock pulse width related.
When you hit the "magic window" (think picoseconds) there is a probability
of going metastable. It's not a 100% thing. Even with multiple synchronizer
stages *not* being metastable is also not a 100% guarantee. 

The real question is - does a once every X seconds / hours / centuries event
bother me in the application? Once you get to a multi stage synchronizer,
the dimensions on the time are large enough that the answer is generally no.
The event is so rare that you will never see it with these data rates. Being
sure it's fixed is easy.

It's the flip side - error rate without the synchronizer that is a bit
harder to quantify. Things could run for weeks outside the threat window. Is
it a several times a minute (every few days) or once an hour (every few
weeks) problem? In the first case, you probably do care. Multiple hits per
minute will mess up the loop. In the second case, you will never notice the
issue. 

Of course, boost the clock, change the logic family, mix logic families,
fiddle this or that and you probably should look at things again...

Bob

-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Bruce Griffiths
Sent: Monday, March 25, 2013 4:38 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Metastability (was Brooks Shera)

Both edges of the 24MHz clock gating pulse are asynchronous with respect 
to the signal being gated.
Metastability can result with clock pulse widths that lie within a 
critical range.

Bruce

Chris Albertson wrote:
> On Mon, Mar 25, 2013 at 12:45 PM, David McGaw<n1hac at alum.dartmouth.org>
wrote:
>    
>> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
>> early 80's.  By the third 7400 generation (F/AS/ALS) the problem was well
>> known with parameters available and the logic fairly hard to it
>>      
> I think this is all moot because as I just wrote in another email the
> PPS signal never gets out of the 74hct4046 chip.   What gets out is
> the output of  "Phase Detector #3".  You've have to know in some
> detail how the 4046 chips' PD3 works.
>
> Chris Albertson
> Redondo Beach, California
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