[time-nuts] Metastability (was Brooks Shera)

Hal Murray hmurray at megapathdsl.net
Mon Mar 25 17:56:25 EDT 2013

n1hac at alum.dartmouth.org said:
> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
> early 80's.  By the third 7400 generation (F/AS/ALS) the problem was well
> known with parameters available and the logic fairly hard to it.

The problem is well understood in the right circles, but we wouldn't be 
having this much of a discussion if it really was widely understood.

The parameters are not readily available.  I've never seen them in data 
sheets.  Sometimes you can find them in app-notes, but those are usually just 
typicals.  I don't remember seeing any worst-case test results.  Peter Alfke 
from Xilinx did a lot of good work in this area.

"Hard" is an interesting term.  In general, settling time scales with the 
general speed of a logic family.  But then designs go faster so there may not 
be any net gain.

The classic solution is a synchronizer: 2 FFs.  Nobody ever does the math 
behind it.  For example, did Bruce's recent comments include any MTBF numbers?

There is a hidden assumption in the classic synchronizer.  The key idea is 
that you need time to allow the first FF to settle.  That means the clock 
must be significantly slower than the max clock rate for the simple FF-FF 
path.  You get that without any thought if you use the same clock for a pile 
of logic that includes something like an ALU.  The time through the ALU is 
the settling time for the synchronizer.

These are my opinions.  I hate spam.

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