[time-nuts] The Trapezoidal Clocking

[Bob Camp]

Hi

If you treat it as a sine, you certainly get further. There are some neat sine wave input chips. The next layer to the problem is that the trapezoid may be slower than (or faster than ) a sine wave depending on just what’s going on with the system. That will make it a bit difficult to know what sort of a clock you have at each tap.

Bob

> On Dec 14, 2014, at 10:40 PM, Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
> 
> Hi,
> 
> Agree. It's not ideal. In it's simplicity it achieves first degree delay compensation, but it is not the best of signals you get.
> 
> You need to treat the signal as being essentially a sine, and overcome the slew-rate.
> 
> It may be a useful technique besides it's limits.
> 
> Cheers,
> Magnus
> 
> On 12/15/2014 03:45 AM, Bob Camp wrote:
>> Hi
>> 
>> 
>> …. but …
>> 
>> 
>> Low edge speeds => poor signal to noise => high jitter.
>> 
>> The result is a clock that aligns, but has high(er) jitter compared to a conventional square wave clock. Most of the “lower phase noise / lower jitter” progress in CMOS logic has gone hand in hand with faster edge rates.
>> 
>> Bob
>> 
>> 
>>> On Dec 14, 2014, at 8:27 PM, Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
>>> 
>>> Bob,
>>> 
>>> On 12/14/2014 02:10 AM, Robert Darby wrote:
>>>> This is an paper that may be of some interest to those interested in
>>>> clock distribution.  The author, Jinyuan Wu has done considerable work
>>>> on FPGA TIC's with Fermi Lab.
>>>> 
>>>> http://www-ppd.fnal.gov/EEDOffice-w/Projects/ckm/comadc/TrapezCLK1b.pdf
>>> 
>>> How incredibly cunning!
>>> 
>>> Cheers,
>>> Magnus
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