[time-nuts] Divide by five
hmurray at megapathdsl.net
Sat Nov 8 04:34:19 EST 2014
> The 74F161 is only rated at 90MHz over temp (TI) and 120MHz or 100MHz
> (unclear) at 25C and then only as "typical" without any max freq being
> indicated at all in the datasheet (Fairchild).
That's just the count frequency. If you want to divide by 5, you have to do
something like use the terminal count output to load it with 15-5.
Unfortunately, the PE (Parallel load Enable) is active low while the TC
(Terminal Count) signal is active high so you have to add an inverter.
Even without the inverter, the clock-out and setup times are way too long.
Clock to out for TC is 10 ns. (typical from Fairchild data sheet)
Setup for PE is 11 ns. (Min at 25C, 5V)
The PAL suggestion was an interesting one. Does anybody have software and/or
a programming setup that still works?
Modern CPLDs or FPGAs would probably work. You can probably get one on a
small board. Not quite a DIP, but might fit. Ahhh. A big DIP. :)
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