[time-nuts] Divide by five

Said Jackson saidjack at aol.com
Sat Nov 8 11:52:30 EST 2014


That means in a divide by 5 you cant even get close to 125MHz even if the  74lvc163 is rated at 200MHz count frequency. Very good point. 

I used to use ABEL with DataIO programmers back in the day, Abel is now licensed by Lattice and I think they still support the old 16V8 and 22V10 types. It is available as freeware from lattice and generates standard Jedec files.

No idea what programmer to use nowadays though, nowadays I use Lattice PLDs with JTAG programmer. Those PLDs can count at 200MHz easily (Lattice 4032 for example).


Sent From iPhone

> On Nov 8, 2014, at 1:34, Hal Murray <hmurray at megapathdsl.net> wrote:
>> The 74F161 is only rated at 90MHz over temp (TI) and 120MHz or 100MHz
>> (unclear) at 25C and then only as "typical" without any max freq being
>> indicated at all in the datasheet (Fairchild).
> That's just the count frequency.  If you want to divide by 5, you have to do 
> something like use the terminal count output to load it with 15-5.  
> Unfortunately, the PE (Parallel load Enable) is active low while the TC 
> (Terminal Count) signal is active high so you have to add an inverter.
> Even without the inverter, the clock-out and setup times are way too long.
>  Clock to out for TC is 10 ns.  (typical from Fairchild data sheet)
>  Setup for PE is 11 ns. (Min at 25C, 5V)
> The PAL suggestion was an interesting one.  Does anybody have software and/or 
> a programming setup that still works?
> Modern CPLDs or FPGAs would probably work.  You can probably get one on a 
> small board.  Not quite a DIP, but might fit.  Ahhh.  A big DIP.  :)
>  http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,798&Prod=CMOD
> -- 
> These are my opinions.  I hate spam.
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