[time-nuts] Time tagging fpga

Bob Camp kb8tq at n1k.org
Sat Nov 22 08:12:46 EST 2014


The key point - it’s a counter after a mixer. You don’t need the fancy delay line / multiple delay line / strange pulse down the delay line stuff in this case. You also don’t wind up with odd algorithms to count bits and determine when a gap really is a gap. In the mix down case, a system running with a 10 MHz clock is normally adequate. A clock rate of 50 or 100 MHz on a simple counter would be overkill in most cases. You get a major error expansion when you down convert the signals. 

Some Math:

Device under test frequency; 5 MHz
Offset oscillator frequency: 5 MHz + 5 Hz
Beat note 5 Hz
Error expansion due to down conversion 1x10^6

If you can resolve edges at 1 second to 1x10^-7 (10 MHz clock) the net resolution would be 1x10^-13. That’s good enough for the sources being used. It improves directly by tau (1x10^-14 at 10 sec) so even if it is marginal at 1 second, it will catch up with any set of real sources somewhere inside 100 seconds In a real system, the limiters on the beat notes are more likely to be the resolution determining factor than a 10 MHz based counter. 

That’s all based on Bill Riley’s DMTD manual and his description of how the box works. It’s also based on the assumption that this one works the same way except the PIC is replaced by the FPGA.


> On Nov 22, 2014, at 3:12 AM, Anders Wallin <anders.e.e.wallin at gmail.com> wrote:
> On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby <bobdarby at triad.rr.com> wrote:
>> I finally got the time tagging fpga I was playing with to a semi-usable
>> state.  I mentioned in an earlier post that I was unable to compile or link
>> the FTDI library but Magnus Karlsson very kindly rewrote a program of his
>> to provide me with a utility to set up the USB asynchronous parallel
>> interface characteristics on the PC.  Only bad thing is you're running
>> blind so it pays to do a short run to make sure all's well before
>> committing to a long capture.
> Interesting! How do you generate a clock (what frequency) for the FPGA?
> Are you using a coarse-counter + interpolator (delay-line?) approach?
> I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which
> has the same fpga used in this work:
> http://arxiv.org/abs/1303.6840
> the VHDL is available on ohwr:
> http://www.ohwr.org/projects/tdc-core/wiki
> Anders
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