[time-nuts] Time tagging fpga
bobdarby at triad.rr.com
Sat Nov 22 10:19:58 EST 2014
The counter runs on a Pipistrello. I looked at the information on the
web about time taggers before starting. I decided to try an
oversampling scheme described by a group of Italian? physicists for a
multichannel time tagging instrument. They used 4x oversampling. My
version is crude; it uses the 50 MHz on-board clock but of course could
use an external clock source. The clock is multiplied to 1 GHz and then
divided into four 125 Hz clocks phased 45 degrees apart. There is a
fifth 125 MHz clock at 0 phase for the main counter and external interface.
There are four channels, each with 3 bits for value and a forth bit
indicating an event. The sixteen bits are followed by a 48 bit counter
The incoming signal is sampled eight times on the positive and inverted
phased clocks. The eight bits are brought back to phase 0 in an eight
stage pipeline. They are decoded based on priority and added to the
front of a 48 bit counter value.
The output is through a 64 bit in, 8 bit out fifo fed to an asynchronous
This yields 1 ns resolution (bin size) but the bins sizes are certainly
not all equal. I have few means to check the accuracy but for my
purposes (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is
certainly more accurate than I need. I have experimented with .5 ns bin
sizes, also using the 8x oversampling with a 250 MHz clock. To keep the
backend 125 MHz structure I used a two phase multiplexer to combine two
successive samples. This runs but is not reliable and needs further work
before it's useful.
Now that I can almost comprehend VHDL I'll take a look at the CERN
project. Certainly the notion of a ± 92 ps tag is interesting.
You are of course correct that nothing fancy is needed. My purpose was
to replace the three PicTic counters in the Riley box with something
that I felt was more reliable. Some time back I posted a question
asking if variable dead time has an effect on ADEV readings. I noticed
very strange variations in the slope of the phase difference as the
counts got close to rollover. I wondered if, as the counter went from
lets say 5 sample/s to 2.5 samples/s and then back, this was a problem.
Based on my first trials, the results appear to be better because there
is no dead time and effectively no phase rollover.
I also wanted to learn about VHDL, VDL, and programmable logic. Know
virtually nothing about the subject, a simple time tagging device that I
could put to some use seemed like a good starting point. But again, for
my purposes the 20 ns resolution of the Pic-Tics was more than adequate.
However, I did think that it might also be useful to compare GPS 1 pps
signals and therefore somewhat better resolution would be useful.
As noted in my post last night, the results feed a binary file. I use
several filter programs to extract the channels and the time difference
between the channels. Any competent programmer (which I am not) could
read the stream in real time and write the differences to an ascii file
for each difference. Assuming three clocks you would then need to
open three instances of Timelab.
Thanks for everyone's help and Jon Mile's Timelab.
On 11/22/2014 3:12 AM, Anders Wallin wrote:
> On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby <bobdarby at triad.rr.com> wrote:
>> I finally got the time tagging fpga I was playing with to a semi-usable
>> state. I mentioned in an earlier post that I was unable to compile or link
>> the FTDI library but Magnus Karlsson very kindly rewrote a program of his
>> to provide me with a utility to set up the USB asynchronous parallel
>> interface characteristics on the PC. Only bad thing is you're running
>> blind so it pays to do a short run to make sure all's well before
>> committing to a long capture.
> Interesting! How do you generate a clock (what frequency) for the FPGA?
> Are you using a coarse-counter + interpolator (delay-line?) approach?
> I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which
> has the same fpga used in this work:
> the VHDL is available on ohwr:
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