[time-nuts] Time tagging fpga

Robert Darby bobdarby at triad.rr.com
Sat Nov 22 10:33:21 EST 2014


I believe the CERN carry chain idea was described in a 2006 paper " A 
High-Resolution Time to Digital Converter Implemented in Field 
Programmable Gate Arrays", Jian Song, Qi An, and Shubin Liu.

Might be interesting to compare the two implementations.

Bob Darby

On 11/22/2014 3:12 AM, Anders Wallin wrote:
> On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby <bobdarby at triad.rr.com> wrote:
>> I finally got the time tagging fpga I was playing with to a semi-usable
>> state.  I mentioned in an earlier post that I was unable to compile or link
>> the FTDI library but Magnus Karlsson very kindly rewrote a program of his
>> to provide me with a utility to set up the USB asynchronous parallel
>> interface characteristics on the PC.  Only bad thing is you're running
>> blind so it pays to do a short run to make sure all's well before
>> committing to a long capture.
> Interesting! How do you generate a clock (what frequency) for the FPGA?
> Are you using a coarse-counter + interpolator (delay-line?) approach?
> I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which
> has the same fpga used in this work:
> http://arxiv.org/abs/1303.6840
> the VHDL is available on ohwr:
> http://www.ohwr.org/projects/tdc-core/wiki
> Anders
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