[time-nuts] Homebrew frequency counter, need help

[Bob Camp]

> On Nov 28, 2014, at 9:18 PM, Angus <not.again at btinternet.com> wrote:
> 
> 
> 
> 
> On Fri, 28 Nov 2014 08:57:37 -0600, you wrote:
> 
>> Hi
>> 
>>> On Nov 28, 2014, at 7:04 AM, Li Ang <lllaaa at gmail.com> wrote:
>>> 
>>> The TDC-GP22 is the best choise for me at the moment. Since I am not a
>>> hardware guy, simplicity is important. It's very cheap in China(About 3$
>>> for each piece ).
>> 
>> Which is a very good reason to play with it 
> 
>> 
>>> 
>>> 
>>> TDC-GP22 has 2 modes and 3 trigger inputs (start, stop1, stop2).  The min
>>> time between start and stop is 3.5ns. max time is about 2.4us.(0 to 2.4 us
>>> between stop channels).
>>> Time resolution is 90ps, or 45ps in double_res mode(1 stop input only), and
>>> 22ps in quard_res mode(1 stop only)
>> 
>> All of which is *plenty* good enough to make a decent counter.  That assumes that they are talking about accuracy (even 1 sigma) rather than just the resolution of the LSB. Specs are often confusing on parts like this. 
> 
> Hi ,
> 
> Unfortunately the 22ps etc is just resolution and there is also a fair
> bit of noise - some typical SD's are given in the data sheet which
> vary from 35 to 72 ps depending on the settings, and that only covers
> part of the range. 60ps RMS noise is also mentioned.
> 
> The nominal clock input is 2-8MHz, but the 22ps range is only
> available for clocks <6MHz, and not in Mode1 which is being used. 
> 
> Should still be enough to give most counters a workout.

Hi

As long as the one sigma point is below 100 ps, that’s not a disaster for turning it into a counter. It’s not going to beat out a SR 620, but it’s still a very respectable device. Being able to do it all with a handful of parts and at 1 to 3% of the cost of a new counter is pretty impressive. 

Assuming that the counter timebase is 10 MHz, a clock into the chip of 5, 3.333, or 2.5 MHz could be done quite easily. It sounds like they all would hit the 2 to 8 MHz range needed. 

Bob


> 
> Angus.
> 
> 
> 
>>> The biggest problem I met:
>>> If you trigger start first, 100ns later stop1, another 100ns later
>>> stop2.Get the result of stop1-start and stop2-stop1. You will find
>>> stop1-start is very unstable(+-2% level) and stop2-stop1 is stable(+-0.1%
>>> level ). Dont know if it's my problem or theirs.
>> 
>> This may be the resolution / accuracy thing I mentioned above. Don’t give up quite yet though. 
>> 
>>> 
>>> Here is the configuration of it (the document is very bad, took me 3 weeks
>>> to play with these 6 registers to get it work as I expected) and schematic.
>> 
>> Gee 
> that sounds like the documentation on a LOT of parts these days
> . It’s also what keeps people from trying this sort of thing. 
>> 
>> A few hardware questions:
>> 
>> 1) What frequency is the crystal at? (can you drive the chip from an OCXO?)
>> 
>> 2) Is there more bypassing on the circuit than shown? (If not, add some more).
>> 
>> 3) How confident are you of your input signal? (can you check it with a “known good” counter?)
>> 
>> 4) Have you tried jumping the 10 ohm resistor on the regulator output? (it may not be helping things 
> )
>> 
>> 
>> A full counter will have a bit more “stuff” than just this chip. I think getting this part working *before* you work on the rest of it is a very good idea. One small piece at a time 
> .
>> 
>> Bob
>> 
>> 
>> 
>>>   Register_0 = 0x00c42700,
>>>   Register_1 = 0x19498000,
>>>   Register_2 = 0xe0000000,
>>>   Register_3 = 0x00000000,
>>>   Register_4 = 0x20000000,
>>>   Register_5 = 0x10000000,
>>>   Register_6 = 0;
>>> 
>>> 
>>> ?
>>> 
>>> 2014-11-28 0:20 GMT+08:00 Tom Van Baak <tvb at leapsecond.com>:
>>> 
>>>> Your project sounds wonderful. The TDC-GP22 has been mentioned only a few
>>>> times over the years and I keep waiting for someone to post actual results
>>>> from this chip, or better yet -- schematics, photos, and source code.
>>>> 
>>>> 
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