[time-nuts] LTE-Lite module
SAIDJACK at aol.com
SAIDJACK at aol.com
Fri Oct 17 21:10:52 EDT 2014
Here is the resulting 10MHz phase noise plot from the 20MHz TCXO output:
In a message dated 10/17/2014 11:32:49 Pacific Daylight Time,
SAIDJACK at aol.com writes:
let me answer through Time Nuts as this may interest other parties as
Yes, using a fast flip flop to generate 10MHz out of the 20MHz TCXO 3.0V
CMOS output from the LTE-Lite module will preserve the phase noise (actually
improve it by up to 6dB due to the 20log(n/m) noise improvement) and will
not add any spurs if you use the clean 3.0V output from the LTE-Lite module
or an external clean power supply (please note the LTE-Lite TCXO RF output
is 3.0V due to the internal 3.3V to 3.0V Low Noise regulator feeding the
TCXO and buffer).
Use fast logic such as 74AC74, 74FCT74, or the like. We do exactly that on
our ULN-2550 boards to generate 50MHz and 25MHz out of the 100MHz, and
using a fast CMOS divider will result in additive phase noise that will be
below the crystal oscillator phase noise floor.
That will result in significantly better phase noise and much lower spurs
than using the synthesized 10MHz output from the board, and one 74' chip
can generate both 10MHz and 5MHz out of the 20MHz LTE-Lite output. This is
exactly what we would do here if we needed a clean 10MHz from the 20MHz
I believe you can order low-noise divide-by-2 blue-top boxes from Wenzel
already packaged-up and connectorized as well.
Hope that helps,
I was one of those looking for 10Mhz but I just thought again now that it
might be just as well to divide the standard 20Mhz output by 2 using a FF.
I think that would preserve all the desirable characteristics of the 20Mhz
signal which I understand to just be square wave at CMOS 3.3v levels
anyway. Is that correct?
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