[time-nuts] GPS-disciplining an ordinary VCXO?

Sun Sep 28 15:00:42 EDT 2014

Mark et. al,

The NEO will have "jitter" or PN that is so large that it cannot be measured with typical phase noise analyzers. Our TSC5125A cannot converge on it for example. This will be 100s to 1000s of times larger than the jitter introduced by your FPGA pins. This is why uBlox et.al don't publish it, its a disaster.

You will not be happy with the performance if you don't filter that jitter even if you only care about 100Hz noise and higher. You have to ask yourself: how do I measure a signal at -130dBc at 2KHz offset if my noise at 20Hz offset is only say -30dBc? What kind of high-pass filter do I need to get rid of that massive close-in phase noise?

Stephane, you will need to replace the analog low-pass filter that follows the phase comparator with a digital low pass filter to get 0.1Hz or lower loop bandwidth. This is what a GPSDO does. A simple PID loop is what accomplishes this typically. The only problem in the analog domain is that the components become unwieldily large below 1Hz and noise etc becomes a real problem, this is why we do the filtering digitally. 

On the thermal sensitivity of that Crystek vcxo: it is slow enough for even a loop with 0.1Hz BW to compensate for it easily if you shield the crystal from airflow. Even a small zip lock bag will slow down the thermal response so much that a 10s loop will easily mask it unless you put the unit right at the outlet of an AC vent, which I recommend not to do.

We have a 1Hz loop-BW product - our RCM board - and I spent a long time designing that analog PLL so I went through the pain of figuring out the best way to do it, with lots of failed experiments. The board locks a very good 10 MHz DOCXO to an external 10MHz reference with about 1Hz BW. Coincidentally that board also has a digital 1PPS loop as a fallback option, as well as a 100MHz ocxo locked to the 10MHz ocxo with a small optimized analog loop BW.

Bye,
Said

Sent from my iPad

On Sep 28, 2014, at 9:40, "Mark A. Haun" <haunma at keteu.org> wrote:

> Hi Said et al.,
> 
> (replying to this instead of your original because I initially forgot
> to turn on mailing-list delivery---been lurking for a while and only
> reading online!)
> 
> I don't have firsthand experience but my sense is that phase noise in
> the 10-100 Hz region is not a huge issue for the radio, i.e., it is not
> a performance requirement to be immune to a strong adjacent signal
> that close to the desired signal.  I definitely don't want to sacrifice
> any PN by the time we are getting beyond a few hundred Hz.  If I knew
> where the PN plots of the NEO and the VCXO crossed, wouldn't that be a
> good starting point for the loop-filter BW?  It would be nice if ublox
> published this :)
> 
> To Bob's question, yes, at room temperature the VCXO moves 300 ppb per
> degree, so I would have thought a loop BW in the 1-10 second range
> would be too slow to follow temperature variations...?
> 
> Regardless of the limits of analog design, a digital implementation is
> attractive because then I could play with the loop filter in a working
> system.  I have space in my FPGA.  Is it as simple as running both
> clocks into the device and implementing dividers + PFD + digital filter
> there?  Anyone have a reference?  My google searches only turn up
> descriptions of the on-chip PLLs, which I think cannot be used without
> also using the on-chip VCO.
> 
> I have read that FPGA IOs introduce considerable jitter; is that less
> of a concern when the loop BW is very narrow and you are averaging over
> thousands of cycles?  The greatest common factor between my clocks is
> 640 kHz so I was thinking to run the PFD at that frequency.
> 
> Regards,
> 
> Mark
> 
> On Sun, 28 Sep 2014 11:23:32 +0200
> Stéphane Rey <steph.rey at wanadoo.fr> wrote:
>> " With that VCXO you want to have a 5s to 10s or more loop time
>> constant (0.1Hz BW) which typically can only be done in the digital
>> domain.."
>> 
>> Hi Said,
>> Could you point us on something describing that ? What kind of
>> digital processing do you think about ?
>> 
>> Cheers
>> Stephane
>> 
>> -----Message d'origine-----
>> De : time-nuts [mailto:time-nuts-bounces at febo.com] De la part de Said
>> Jackson via time-nuts Envoyé : dimanche 28 septembre 2014 07:50
>> À : Discussion of precise time and frequency measurement
>> Cc : time-nuts at febo.com
>> Objet : Re: [time-nuts] GPS-disciplining an ordinary VCXO?
>> 
>> Mark,
>> 
>> In the analog domain you can probably do a PLL with a 1Hz loop BW.
>> Using a PLL chip like ADF 4002 or similar. This means all the nasty
>> noise from the NEO will taint your PN up to 20Hz or more, very
>> significantly close-in. If you don't care about noise (jitter) below
>> 100Hz then this is fine. If you do as it will dominate your ADC
>> jitter then you can't use an analog PLL.
>> 
>> With that VCXO you want to have a 5s to 10s or more loop time
>> constant (0.1Hz BW) which typically can only be done in the digital
>> domain.. This allows you to use the excellent 1Hz to 100Hz PN of that
>> VCXO without tainting it by the noisy NEO.
>> 
>> An even better setup would be to lock a very low noise 5 or 10MHz
>> ocxo to the GPS with >100s time constant, then use the analog PLL
>> with wider bandwidth (say 30Hz) to reduce the VCXO PN close-in even
>> further by using the ocxo to supress the vcxo PN.
>> 
>> Welcome to our world, if you look at the archives there are 10++
>> years of discussions about exactly doing this...
>> 
>> Bye,
>> Said
>> 
>> 
>> 
>> Sent from my iPad
>> 
>> On Sep 27, 2014, at 21:01, "Mark A. Haun" <haunma at keteu.org> wrote:
>> 
>>> In my quest to learn Verilog and get my hands dirty with 
>>> software-defined radio, I'm currently designing a direct-sampling 
>>> shortwave receiver.  This uses an 80-MSPS ADC, which requires a 
>>> low-phase-noise oscillator, e.g. Crystek CVHD-950 or Abracon
>>> ABLNO. It would be nice to have some provision for locking this
>>> oscillator to an external reference, hence my question:
>>> 
>>> All of the amateur GPSDO designs I've seen are disciplining an
>>> OCXO. I understand this is easier because the excellent short-term
>>> accuracy of the OCXO means the feedback can run slower, so even a 1
>>> PPS signal can be used.
>>> 
>>> I am wondering what sort of performance could be achieved by 
>>> disciplining my VCXO directly with a good GPS module.  I have a
>>> NEO-7N (Ublox) with configurable timepulse up to 10 MHz.  Someone
>>> mentioned that this is derived from 48 MHz, so jitter is reduced if
>>> you pick an integer divisor.  That is fine, but I don't have a feel
>>> for what other irregularities may be present in the timepulse
>>> output, and how they would affect the performance.  I also don't
>>> know how to go about designing a PLL loop filter.  I understand the
>>> goal is to marry the long-term GPS stability with the short-term
>>> VCXO stability but all I have is a phase-noise plot for the VCXO.
>>> How do you know where to split the difference?
>>> 
>>> It is not essential to the larger project, but what I am ideally
>>> going for is 1 ppb frequency match between two ends of a radio
>>> link, and 1 ppb stability over data symbol times.  That is, carrier
>>> stability of ~ 1/10 cycle at 10 MHz over one-second symbols.
>>> (Channel coherence imposes this limit.)  I know the experts here
>>> can tell me whether this is impossible, totally doable, or
>>> somewhere in between!
>>> 
>>> Thanks,
>>> 
>>> Mark
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