[time-nuts] GPS-disciplining an ordinary VCXO?
haunma at keteu.org
Mon Sep 29 13:36:08 EDT 2014
Said, would you suggest implementing the dividers and PFD in the FPGA, along
with the digital filtering? Or feeding the FPGA with some version of the
PFD output? I am trying to avoid an extra A/D step here, but I have no
experience with it. Post-filter, I am satisfied that a simple one-bit D/A
with passive filtering will get me to 16 bits resolution for the VCXO
control, enough for ppb resolution.
Thanks for the data point on the vcxo thermal sensitivity; it's very useful!
Said Jackson [saidjack at aol.com] wrote:
> Stephane, you will need to replace the analog low-pass filter that follows
> the phase comparator with a digital low pass filter to get 0.1Hz or lower
> loop bandwidth. This is what a GPSDO does. A simple PID loop is what
> accomplishes this typically.
> On the thermal sensitivity of that Crystek vcxo: it is slow enough for
> even a loop with 0.1Hz BW to compensate for it easily if you shield the
> crystal from airflow.
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