[time-nuts] GPS-disciplining an ordinary VCXO?

Mark Haun haunma at keteu.org
Tue Sep 30 13:09:22 EDT 2014

Hi Hal,

I'm familiar with 1-bit D/As and plan to use something a bit more evolved
than the MCU/counter approach.  I am already working in an FPGA as that is
absolutely required to deal with the 80-MSPS 16-bit radio data stream. 
(This is an SDR project first, a GPSDO project second, or maybe third or

It was the other end of the PLL I was hoping to get some pointers on. 
Specifically, I can implement the dividers and the standard double-flip-flop
PFD, but what best replaces the charge pump in a fully-digital
implementation?  I will have down/up signals which are asynchronous to the
clock inside the FPGA, and need to get from that, to numbers which can be
filtered.  Some kind of counter perhaps?  Pointers to any examples or papers
would be appreciated... my googling didn't turn up anything.


Hal Murray [hmurray at megapathdsl.net] wrote:
> haunma at keteu.org said:
> > I am trying to avoid an extra A/D step here, but I have no experience with
> > it.  Post-filter, I am satisfied that a simple one-bit D/A with passive
> > filtering will get me to 16 bits resolution for the VCXO control, enough for
> > ppb resolution.
> One bit D/As need a filter.  The stuff that gets through the filter turns 
> into spurs.  Are you OK with that?
> 16 bits at 10 MHz is 6553.6 microseconds or 152 Hz.  (and harmonics)

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