[time-nuts] GPS-disciplining an ordinary VCXO?

[Hal Murray]

haunma at keteu.org said:
> It was the other end of the PLL I was hoping to get some pointers on.
> Specifically, I can implement the dividers and the standard double-flip-flop
> PFD, but what best replaces the charge pump in a fully-digital
> implementation?  I will have down/up signals which are asynchronous to the
> clock inside the FPGA, and need to get from that, to numbers which can be
> filtered.  Some kind of counter perhaps?  Pointers to any examples or papers
> would be appreciated... my googling didn't turn up anything.

How about this...

An analog charge pump just dumps charge into a capacitor.  The digital 
equivalent of a capacitor is a counter.

Think of the output of the (digital) charge pump as +1, 0, and -1 so the 
counter goes up, hold, or down.

If you are locking to the PPS rather than 10 MHz, you can get a multibit 
sample.


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