[time-nuts] FLL errors
azelio.boriani at gmail.com
Fri Aug 28 18:37:10 EDT 2015
If FLL: something that links frequencies,
PLL: something that links phases,
frequency detector: output proportional to frequency error,
phase detector: output proportional to phase error (XOR),
and the original question (about FLL) was how to implement a simple FLL,
can an FLL be made by a phase detector? Can a PLL be made by a
Phase_detector_XOR + RC + VCO-> FLL: equal frequencies, phase linked
to VCO odds,
in this case the frequency error is 0.
On Fri, Aug 28, 2015 at 7:14 PM, Charles Steinmetz
<csteinmetz at yandex.com> wrote:
> Azelio wrote:
>> OK: the XOR gate with an RC is a defective PLL and a defective FLL. It
>> is a simple way to have an idea of what an xLL should be but of no
>> serious use.
> No, not at all. I was suggesting that the XOR PLL you were commenting on
> had problems.
> First, an XOR with or without an RC is not an FLL at all, of any sort.
> Second, the XOR gate is a time-honored phase detector for PLLs, and if its
> limitations are understood and accounted for, it makes a perfectly
> serviceable PD for a PLL. There are other phase detectors that are more
> popular these days, for a variety of reasons, but the XOR works just fine in
> a proper design.
> See, e.g.:
> Best, Phase-Locked Loops (2007), pp. 16-18
> Gardner, Phaselock Techniques (3rd ed) (2005), pp. 245-46
> Wolaver, Phase-Locked Loop Circuit Design (1991) pp. 55-59
> and many, many, many others.
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