[time-nuts] FLL errors

Charles Steinmetz csteinmetz at yandex.com
Sat Aug 29 00:11:00 EDT 2015

Azelio wrote:

>can an FLL be made by a phase detector?

No (not using a PD as the primary detector).

>Can a PLL be made by a frequency detector?

No (not using an FD as the primary detector).

>Phase_detector_XOR + RC + VCO-> FLL: equal frequencies,
>phase linked to VCO odds, in this case the frequency error is 0.

Well, yes, if a PLL is locked the frequency is, by definition, also 
locked.  Conversely, if an FLL is locked, the phase error will only 
be zero every now and then.  (And if a PLL is not locked, it is very 
unlikely that the frequency will be correct -- the loop will most 
likely eventually force the VCO to one end or the other of its range.)

Understand that actual PLLs and FLLs are not perfect -- there will 
always be some residual phase (PLL) or frequency (FLL) error, because 
the loop gain is not infinite.  You want these errors to be small, 
and stochastically distributed equally on both sides of zero, by design.

PLLs are not subject to the same kinds of systematic frequency errors 
that plague most hobbyist FLLs.  Of course, they have their own 
problems, the main one for hobbyists being that they require loop 
filters with VERY long time constants (hundreds to thousands of 
seconds), so they cannot practicably be realized with analog RC 
circuits.  Most hobbyists do not have the knowledge or resources to 
design adequate digital loop filters, so they build FLLs instead 
(and, as we have seen, their designs very often have residual 
frequency errors because they failed to address the systematic errors 
and did not shape the remaining errors with dithering).

Best regards,


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