[time-nuts] FLL errors

Magnus Danielson magnus at rubidium.dyndns.org
Sat Aug 29 04:47:51 EDT 2015

I think you put too much into the detector without concerning the rest 
of the design. The XOR gate is a 1-bit multiplier. If you have nice and 
clean "digital" signals, it is a good choice.

What makes a PLL or FLL a poor design is not down to only the detector, 
it is also to the rest of the design. Using a simple low-pass filter is 
possible, but doesn't make a good PLL or FLL. A poor FLL only has a 
gain-stage, or act as if it only had a gain stage, and then the gain 
will determine out of the unsteered frequency difference /|f0, the 
remaining frequency difference /|f is /|f0 / G. Similarly in a poor PLL, 
the gain will determine how large phase error it takes to generate the 
frequency correction.

Using an integrator to build up the state for frequency error, FLLs goes 
towards biases in frequency errors and PLLs goes into biases in phase 
errors. You want to control the damping in PLLs, so you end up with a PI 
loop controler.

There is tricks being played with phase-detectors to make the frequency 
and phase-lock quicker, more stable etc. You can play with heuristics 
and you can play with parameter settings. Playing with the detector part 
is only one out of many tricks.

I've been ashamed of larger design errors than using a XOR gate, let me 
tell you.

Warren did a nice design that unwrapped XOR gates to form a sawtooth 360 
degree detector rather than the normal 180 degree triangular detector.

As for noise into any form of "digital" detector having non-sine 
response, it will degrade the detector into a sine-like response.


On 08/28/2015 12:16 PM, Azelio Boriani wrote:
> OK: the XOR gate with an RC is a defective PLL and a defective FLL. It
> is a simple way to have an idea of what an xLL should be but of no
> serious use.
> On Fri, Aug 28, 2015 at 5:03 AM, Charles Steinmetz
> <csteinmetz at yandex.com> wrote:
>> Azelio wrote:
>>> Since I have not found a strong definition for the FLL, I assumed: if
>>> PLL= zero phase error (and so zero frequency error) the FLL= same
>>> frequency, random phase. The XOR with RC is a perfect fit for this:
>>> same frequency all the time but phase determined by the EFC needed to
>>> have that frequency. The phase = constant, in the XOR/RC is true as
>>> long as the VCO is stable and the EFC has not to be altered to steer
>>> the VCO, that constant is not a design parameter but walks with the
>>> VCO frequency movement.
>> The "x" in "xLL" refers to the parameter that is measured, which the "LL"
>> attempts -- more or less successfully, depending on the particular
>> implementation -- to drive to zero.  (More correctly, the "LL" attempts to
>> drive the measured quantity to a constant.  Many PLLs do not lock with the
>> controlled oscillator at 0 phase relative to the reference oscillator, they
>> lock near 90 or 180 degrees.  This includes PLLs with XOR phase detectors,
>> which lock with the VCO at ~90 degrees to the reference oscillator.)
>> An XOR measures the *phase* difference between two oscillators, and an xLL
>> with an XOR detector is, therefore, a PLL.  If it is incapable of locking
>> stably, that does not make it an FLL -- it is just a defective PLL.
>> An FLL measures the *frequency* difference between two oscillators and
>> attempts to drive it to zero.  (As I mentioned in my previous post, because
>> of systematic biases, the FLL actually drives the frequency difference to a
>> low value near zero.  Carefully engineered dither can be added to
>> redistribute the error stochastically around zero.)
>> Best regards,
>> Charles
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