[time-nuts] 4046 experiment for gpsdo

Jim Harman j99harman at gmail.com
Fri Sep 25 14:11:46 EDT 2015


Hi Can,

I suppose your circuit will work as you describe, but the diode-R-C network
at the output of the HC4046 followed by an A/D converter works fine if your
application is to lock an oscillator to a reference and you don't care if
there is a constant time (phase) difference between the two when locked.

The key is that instead of trying to reduce the time difference to zero,
you define a setpoint near the middle of the range of the phase comparator.
You then adjust the frequency of the oscillator to keep the phase
comparator output near the setpoint.

Using PC3, 1 MHz for the oscillator, and 1 PPS for the reference, you will
get a pulse 0-1 usec wide. If you have a 10 bit A/D converter reading the
height of the integrated pulse, you get 1 nsec resolution, which is at
least 10x better than anything you will get from an all-digital solution
counting clock cycles. Defining the setpoint at 500 A/D counts in the
filter algorithm will control the oscillator so it is nominally 500 ns
ahead of the reference.

On Fri, Sep 25, 2015 at 2:18 AM, Can Altineller <altineller at gmail.com>
wrote:

> Hello All,
>
> I got a CD74HC4046 and started to experiment. It seems that this is a newer
> version, which has another phase comparator instead of the zener diode.
> There has been some changes in the chip basically. PC1out is a xor gate,
> and PC3out is an RS flip flop. It will give pulses if one source is behind,
> and it will give reverse pulses if one source is forward. PP pin gives the
> reverse of every phase differences corresponding to a rising edge, so it is
> half the xor pulses in frequency.
>
> I made the following circuit on breadboard:
>
>
>> 1PPS pulses from both RTC and SYNC source gets inverted, (because we are
> interested in falling edges) - Signal and comparator pins of 4046 is fed
> with those pulses. The PC1 out is a XOR phase pulses, for both rising and
> falling edges, so we are only measuring it for display purposes on the
> following images.
>
> P3Out gives a pulse, if source is behind it will give a sharp pulse from 0
> to logic 1 voltage, and if source is forward it will be at logic 1 voltage,
> and give a sharp drop. (On the circuit above the 4046 has no zener, but PC3
> instead).
>
> The PP output from 4046 inverted gives as the phase pulse, no matter if it
> is lacking or forward it will give the same normal pulse. By using and
> gates and getting
> !PP & PC3Out gives us forward pulse, and !PP && !PC3Out gives us reverse
> pulse.
>
> Here is a logic analyzer capture of XOR, Forward pulse and reverse pulse,
> when the RTC is behind.
>
>
> And here Source is behind
>
>
>
> So in summary, we get pulses from one pin saying that the RTC is behind,
> and if RTC is forward it will pulse from the other pin. I will now proceed
> to feed these pulses into the RC network.
>
> I got this far tru experimentation with the 4046. The VCO can also be
> inhibited for low power consumption, (since we are only using the phase
> comparators)
> I tried a lot of logic circuits to cover a generalized case of the phase
> difference between clock pulses, but now I want to make a hybrid algorithm
> which will work with interrupts until within certain range steering the
> clock in to the zone, and then it might tune from the RC networks. (I would
> use two of them, for increasing and decreasing the oscillator)
>
> I would love to hear your comments for the above circuit because I might
> have overlooked something major, that will screw up the operation.
>
> Best Regards,
> Can
>
>>
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-- 

--Jim Harman


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