[time-nuts] Fw: Commercial software defined radio for clock metrology

Sat May 28 04:36:16 EDT 2016

The FPGA is probably adequate (if it has LVDS inputs), but a dual single chip ADC is also required.
Bruce

     On Saturday, 28 May 2016 5:05 PM, Bob Stewart <bob at evoria.net> wrote:

 Hi Bruce,

What about the BeMicroCV-A9 that Scotty Cowling has been recommending in QEX?  It has a Cyclone V SoC FPGA running at 800MHz.  Installments to his series have been slow coming, but I've been wondering if this could be the basis for a Timepod type of unit.

Bob

--------------------------------------------
On Fri, 5/27/16, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:

 Subject: Re: [time-nuts] Commercial software defined radio for    clock    metrology
 To: "Discussion of precise time and frequency measurement" <time-nuts at febo..com>
 Date: Friday, May 27, 2016, 10:08 PM

 The Red Pitaya FPGA may
 be a little too small.Its not clear if a single chip ADC is
 used.If not, the performance will suffer.Dc coupled inputs
 will degrade the performance somewhat compared to
 transformer coupled inputs.

 Input bandwidth would be around 40MHz or so for
 the Nyquist band of interest.The output bandwidth used was
 something like 100 kHz.
 Bruce

     On
 Saturday, 28 May 2016 2:01 PM, Hal Murray <hmurray at megapathdsl.net>
 wrote:

 bruce.griffiths at xtra.co.nz
 said:
 > All the filtering and down mixing
 is done in the digital domain.
 >
 Anitialiasing filters in front of the ADCs are also be
 required. 

 What sort of
 bandwidth is expected?

 The
 usual trick with audio ADCs is to have a low cost analog
 filter that 
 does't have a sharp corner
 but lets everything you want through, sample at a 
 high rate - say 16x, run that through a digital
 filter with a sharp cutoff, 
 then decimate
 down to the desired sample rate.

 -- 
 These are my opinions.  I
 hate spam.

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