[time-nuts] 1PPS to 32.768 khz

David davidwhess at gmail.com
Wed Oct 19 23:07:20 EDT 2016

I was thinking 32.768kHz VCXO and phase detector to make a simple
analog PLL.  I found a datasheet for a suitable VCXO and assuming a
total error of 20ppm, it would only need to be divided by 2 to prevent
locking to the wrong frequency making an analog PLL pretty simple.
Safer to divide by 4 or 16 of course.

But I wonder if a microcontroller using a 32.768kHz external clock
could be the phase detector itself.  Strobe the microcontroller ADCS
from the 1 PPS to sample the sine 32.768kHz clock, simmer, and serve.
Or just count cycles to make a FLL.

The most annoying thing about using a varactor for tuning is that they
are not amendable to low drive voltages.

On Wed, 19 Oct 2016 18:14:32 -0400, you wrote:

>As has been already mentioned, a lot depends on what you have. The drop dead cheapest way to do it:
>Start with an MCU with an internal oscillator. There are *lots* to pick between. Which sort really does not matter. 
>For example, I’ll use one that starts at 4 MHz. 
>Divide the 4 MHz down to 32,768, or as close as you can get. The common clocks aren’t going to divide
>straight to 32768 so you will need to do two divides. One will be a bit fast, the other a bit slow. You flip between the 
>two in a fixed pattern to get the result to average out correctly. 
>Next take the same 4 MHz and run a counter /timer off of it. Capture the pps edge with the timer. It will drift
>a bit since the clock in the MCU is not perfect. Based on the drift, modify your dividers to correct the outcome. 
>If you are “good” to 1 part in 32,768 in each second, that’s close enough for a wall clock. You will have no net
>error long term if you do it right. 
>That’s all a sub $1 solution

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