[time-nuts] PLL Digital Loop Filter

[Alex Pummer]

it is tempting to use digital loop filter for PLL if a very low 
bandwidth is required, but with the large time constant is a problem ; 
the VCO will change it's frequency despite the tuning voltage remains 
constant and that is not so simple to model.

73

KJ6UHN

Alex


On 3/21/2017 4:39 AM, Attila Kinali wrote:
> On Mon, 20 Mar 2017 21:32:28 -0700
> James Peroulas <james at peroulas.com> wrote:
>
>> I'm trying to understand how to design and analyze the loop filters in a
>> digital PLL. Specifically, because of digital processing delays, the phase
>> offset measured at time t will only produce a change on the VCXO input at
>> time t+T, where T is the sampling period of the digital loop.
> You have the same delays in analog filters as well. As a rule of thumb
> you can assume that the delays are in the same order of magnitude as
> with the equivalent analog filters, not accounting for the delays due to
> pre- and post-processing of the signal.
>   
> The analysis of digital PLLs works the same as with analog ones, you
> just exchange the Laplace transform with the Z-transform. You can add
> arbitrary delays due to pre/post-processing as a simple multiplication
> by 1/z for each clock cycle of delay.
>
>> I've found plenty of texts describing analog loop filters. Are there any
>> recommendations for digital loop filter PLL design?
> The PLL book by Best contains two chapters on how to design digital PLLs.
> I can also recommend "Understanding digital signal processing" by Lyons,
> which is a very hands-on description how to do filters and perform other
> signal processing tasks.
>
>
> 				Attila Kinali
>