[volt-nuts] PWM voltage divider

Vince Mulhollon vince at mulhollon.com
Wed Jan 8 07:53:07 EST 2014

On Wed, Jan 8, 2014 at 3:38 AM, Ulrich Bangert <df6jb at ulrich-bangert.de>wrote:

> with standard PWM generated from a microcontroller the repetition rates of
> the signal may get VERY slow with higher resolutions, making it difficult
> to
> make a pure DC signal from. <volt-nuts-bounces at febo.com>

As a tradeoff if you're willing to not use hardware PWM, or if you're very
careful about controlling it anyway, you can look at how a very long phase
register works in a DDS ckt with a D/A having much fewer bits.  So it only
outputs a crude 8 bits or whatever but a very long register accumulates and
gradually corrects for error, at substantial phase noise cost of course.

Lets say in a FPGA you drive it at 100 MHz and have a 32 bit PWM counter.
That means a cycle time of 42 seconds which is awful (at half scale, how
many capacitor time constants is 21 seconds?  Or rephrased, assuming you
create a RC ckt with a 210 second RC constant, what, maybe a 2100 second
settling time aka a little less than a half hour?).  But what if you drove
a 16bit counter at 100 MHz?  Ah about half a millisecond.  Not so hard to
filter a 1 KHz square wave into 0.5 DC.  But at 3 bits/digit that 16 bit
PWM is scarcely 5 digits, eh just use a 6/7 digit KVD, simpler, more
accurate, more precise, and cheaper.  However there is a way around that...
you dither the PWM parameters on a regular controlled basis.  So all the
time you run 32768 counts, or half the time 32768 and half 32769 counts, or
all the time 32769 counts, tada at some considerable software complexity
you've built a 17 bit PWM D/A.  Now the 1 KHz "noise" that needs to be
turned into DC has a lot of phase noise, or theres a low freq component on
the spectrum analyzer.  So there's ways at the cost of some hardware and
software complexity to trade excellent repetition rates for truly awful
phase noise.

I've been fooling around with the idea of digitally generating wideband
white noise in a FPGA and then doing all the traditional DSP stuff to shift
the level up and down and even compensate at least partially for my
probably rotten "RF" to DC detector.  In the 80s (well, late 80s) I used an
8 bit sound blaster and generated .wav files (considerably slower than real
time, I'm sorry to say) that semi-controllably when fed thru a
rectifier-capacitor could make controllable DC voltages that varied to a
much smaller resolution than I had a multimeter to measure.  Of course the
settling time of the RC ckt was awful.  Also the non-linearity of the
rectifier probably vastly exceeded the possible precision of the digital
system.  I could have made some kind of synchronous controlled rectifier
using a fet that would have worked better, but...

Of course you've just turned a relatively simple DC voltage divider
problem, into a not too simple timing source problem AND a complicated
programming problem AND a complicated RF problem, so its more for "fun".

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