[volt-nuts] Building a high resolution DAC

Andreas Jahn Andreas_-_Jahn at t-online.de
Mon Aug 17 11:04:25 EDT 2015


Hello,

see my comments on the cirquit [1] here:
https://www.febo.com/pipermail/volt-nuts/2010-October/000537.html

So it will get very hard to go below 1ppm linearity. (without a 
exact/calibrated feedback loop).
Since the formula in the article is wrong you will need some overlapping 
bits anyway.

With best regards

Andreas


Am 17.08.2015 um 15:16 schrieb Attila Kinali:
> Hi,
>
> I have been pondering how to build a high resolution DAC over the weekend.
> Something like [1] but has the disadvantage of needing a pair of resistors
> that have a 1:2^16 ratio. The 1M/15.4R is kind of unwieldy.
> Fidling around a bit, I came to the conclusion that using an R-100R ladder
> with 4 10bit PWM DACs would be a good solution. 100R and 10k resistors
> are readily available in 0.1% 25ppm/°C (and actually quite cheap).
> While the first stage gives 10bits, each additional stage gives
> approximately another 7bits, resulting in a total of 29bits resolution.
> The 3 remaining bits per stage can be used to linearize the whole
> circuit.
>
> Now this is where the problem starts. How do I measure the circuitry
> to build a linearization table? The linearity error is dominated by
> the first stage error which is in the order of 0.1% and thus 10bits.
> It would be necessary to measure this to somewhere close to 29bits, but
> the best DACs that are readily available are 24bit. Yes, there is the
> possibility to build some ADC that could do 28bit, but I am not exactly
> keen on building something aking an HP3458 (mostly to avoid the
> embarrasment of failing at doing so).
>
> So, the question is how would one calibrate something like this?
> Or am I missing something fundamental here?
>
>
> Thanks in advance
>
> 			Attila Kinali
>
> [1] "DC-accurate 32-bit DAC achieves 32-bit resolution",
> by Stephen Woodward, 2008
>



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