[time-nuts] Digital tight PLL method
warrensjmail-one at yahoo.com
Mon May 24 16:48:45 UTC 2010
Concerning the simple, $10, Low cost, Tight PLL method of doing ADEV.
"If you accept that the measurement is going to be limited by the Reference
Then for Low COST and SIMPLE, with the ability to measure ADEVs at very low
Can't beat a simple analog version of NIST's "Tight Phase-Lock Loop Method
of measuring Freq stability".
http://tf.nist.gov/phase/Properties/one.htm#oneone Fig 1.7"
Here is some more information on the subject that may help inspire some of
the great minds out there.
In spite of all the unjustified criticism, the latest test will show, at
least to the more open minded nuts,
There is NOTHING inherently wrong with the tight PLL method as I have done
it. It gives about as good of answers as anything out there.
As I've implemented it, there are some disadvantages, because there is just
so much one can do with a single Op amp design.
If one does the calculation they will also see the OP amp is not a limiting
factor in the performance of this method.
AS I have said before, the disadvantage of my simple BB version that was
tested, is that it is limited by the Ref Osc and the way it's freq is
The accuracy is limited by the fact the first simple BB version I built is
an all analog system.
That is solely because the frequency control I used on the simple version is
the analog EFC input of the reference Osc.
I've also pointed out, that is not a limitation of the method, there are
solutions for that.
Now I'm amazed that no one has had a New inspiration.
Maybe a more direct approach will help some to see the next logical step.
Using the same basic tight PLL method, make some of the unit digital.
Do not modify the freq of the reference osc with analog, GET it yet?
That way the device would be half digital without any of the analog
shortcoming or the need to physically change the reference freq.
Do I really need to explain more?
More information about the time-nuts